In recent years, a data signal is transferred in a DDR format between chips or between modules. In the DDR format, the data signal is processed with the both timing of a rise edge and a fall edge of a clock signal. Therefore, transferring the data signal in the DDR format can improve a transfer rate.
Before explaining the present invention, a conventional example of a circuit (input circuit) receiving a data signal in a DDR format will be briefly described with reference to FIG. 4.
As shown in FIG. 4, the input circuit for a data signal in a DDR format is generally constituted of a variable delay device (VD) 10, a first flip-flop (first F/F) 1, a second flip-flop (second F/F) 2, a third flip-flop (third F/F) 3 and a fourth flip-flop (fourth F/F) 4.
A data signal in a DDR format is inputted to the variable delay device. Further, the first F/F 1 fetches a delayed data signal outputted from the variable delay device 10 in synchronization with a clock signal. That is, the data signal is fetched with a timing of a rising edge of the clock signal.
Furthermore, the second F/F 2 fetches the delayed data signal in synchronization with a reverse clock signal obtained by reversing the clock signal. That is, the data signal is fetched with the timing of a fall edge of the clock signal.
Therefore, a phase of the data signal outputted from the second F/F 2 is delayed from a phase of the data signal outputted from the first F/F 2 by a ½ cycle of the clock signal.
Thus, the third F/F 3 fetches an output signal from the first F/F 1 in synchronization with the clock signal. Moreover, the fourth F/F 4 fetches an output signal from the second F/F 2 in synchronization with the clock signal. Since the third and fourth F/F 3 and 4 respectively fetch output signals in synchronization with the clock signal in this manner, the output signal of the first F/F 1 and the output signal of the second F/F 2 can be in phase.
Meanwhile, the data signal in a DDR format is transferred at a high speed. Therefore, in the DDR format, an allowable range of a skew (signal phase shift) between the data signal and the clock signal is very narrow. Thus, in the input circuit, the skew is corrected by delaying the data signal by using the variable delay device 10.
Here, setting a delay time at the time of initialization can be performed by giving predetermined data and a clock as pattern data, gradually changing a delay time of the variable delay device 10 and reading output values of the first and second F/F 1 and 2 each time.
As shown in FIG. 4, the conventional input circuit includes a first AND circuit 11 to which the output signal from the first F/F 1 and a read mode signal are inputted and a second AND circuit 12 to which the output signal from the second F/F 2 and the read mode signal are inputted, thereby reading output values of the first and second F/F 1 and 2.
The output values are read in the following manner. First, the input circuit is operated for a predetermined clock number given from the pattern data, and predetermined data signals are outputted from the variable delay device 10. The outputted data signals are held in the first and second F/F 1 and 2. The clock signals whose number is equal to a predetermined pattern number are generated, and this generation is then terminated (stopped). The data signals held in the first and second F/F 1 and 2 are respectively read through the first and second AND circuits 11 and 12 based on the read mode signals.
Then, the read values and the data signals are compared, and it is judged whether they have been correctly fetched into the first and second F/F 1 and 2, respectively. If the data signals have not been correctly fetched, a delay time is increased in increments of a predetermined time, and the judgment is repeated. Then, a skew is corrected, and a delay time with which the data signals can be correctly fetched is set.
As described above, in the conventional input circuit, since the first and second F/F 1 and 2 judge whether the data signals have been correctly fetched, the clock signals as pattern data must be generated every time the setting of the delay time is changed and judged. Therefore, besides the circuit configuration shown in FIG. 4, a program, a circuit or the like which generates and controls the clock signals as the pattern data is required.
In view of the above-described problems, it is, therefore, an object of the present invention to provide a phase correction circuit capable of easily detecting a skew between a data signal and a clock signal and correcting their phase difference without requiring a clock signal as pattern data upon initialization.